Cadence Announces New Low-Power IP for PCI Express 5.0 Specification on TSMC N5 Process
25 May 2021 - 12:45AM
Business Wire
Long-reach, high-performance PCIe 5.0 IP with
ultra-low power consumption targets hyperscale computing,
networking and storage applications
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced
immediate availability of Cadence® IP supporting the PCI Express®
(PCIe®) 5.0 specification on TSMC N5 process technology. The next
follow-on version on TSMC N3 process technology is expected to be
taped out in early 2022. Collaboration with major customers is
ongoing for N5 SoC designs targeting hyperscale computing and
networking applications. The Cadence IP for PCIe 5.0 technology
consists of a PHY, companion controller and Verification IP (VIP)
targeted at SoC designs for very high-bandwidth hyperscale
computing, networking and storage applications. With Cadence’s PHY
and Controller Subsystem for PCIe 5.0 architecture, customers can
design extremely power-efficient SoCs with accelerated time to
market.
The Cadence IP for PCIe 5.0 architecture offers a highly
power-efficient implementation of the standard, with several
evaluations from leading customers indicating it provides industry
best-in-class power at the maximum data transfer rate of 32GT/s and
worst-case insertion loss. Leveraging Cadence’s existing N7/N6
silicon validated offering, the N5 design provides a full 512GT/s
(gigatransfers per second) power-optimized solution across the full
range of operating conditions with a single clock lane.
In conjunction with Cadence’s low-latency Controller IP for
Compute Express Link™ (CXL™), the Cadence PHY IP for PCIe 5.0
technology enables a new class of applications for cache-coherent
interconnects for processors, workload accelerators and memory
expanders, as well as support for a wide range of Ethernet
protocols. This provides flexible use cases for systems that need
to leverage the same IP for the networking class of applications.
Cadence is at the forefront of PCIe 5.0 subsystem interoperability
testing, working with all major PCIe test equipment vendors for
protocol and electrical compliance.
“We are pleased to see Cadence expanding its IP family to
support the PCIe 5.0 protocol on TSMC’s advanced processes,” said
Suk Lee, vice president of the Design Infrastructure Management
Division at TSMC. “Our close collaboration with Cadence will help
our mutual customers meet the stringent power and performance
requirements and accelerate silicon innovation with leading-edge
design solutions benefiting from TSMC’s advanced technologies.”
“Increasingly, our customers are demanding not just point IP,
but total solutions that provide an edge by shortening development
timeline and accelerating end-product deployment. The addition of
the ultra-low power PCIe 5.0 solution to our portfolio of
high-performance IP on the TSMC N7/N6, N5 and N3 technologies
fulfills this need,” said Sanjive Agarwala, corporate vice
president and general manager of the IP Group at Cadence. “Our
close collaboration with TSMC ensures that we can continue to
develop advanced IP on TSMC’s most advanced processes. We’ve been a
key provider of leading-edge PHY IP for more than 10 years and have
one of the most experienced PHY design teams in the industry.
Developing a solution with such low power for PCIe 5.0 architecture
is a testament to the innovation our engineering teams can bring to
bear to support our high-performance customer base.”
“Cadence’s PHY and controller test chips for PCIe 5.0 showed
robust performance in compliance tests on our Xgig exerciser and
analyzer platform,” said Tom Fawcett, vice president and general
manager, Lab & Production Business Unit, VIAVI Solutions.
“Collaboration with industry leaders and visionaries like Cadence
is the key to building ecosystem confidence in—and rapid adoption
of—the new protocol.”
“As a long-standing PCI-SIG® member, Cadence has played a role
in promoting the adoption of PCIe technology,” said Al Yanes,
president and chairman of PCI-SIG. “With its continued investment
and innovation in PCIe IP, Cadence is one of the member companies
enabling the latest standards to be available for widespread
deployment.”
The Cadence IP for PCIe 5.0 architecture supports the company’s
Intelligent System Design™ strategy, which enables advanced-node
SoC design excellence. Cadence’s comprehensive portfolio of design
IP solutions in the TSMC advanced processes also includes 112G,
56G, die-to-die (D2D) and advanced memory IP solutions. For more
information on the Cadence IP for PCIe 5.0 technology, please visit
www.cadence.com/go/pcie5pr.
About Cadence
Cadence is a pivotal leader in electronic design, building upon
more than 30 years of computational software expertise. The company
applies its underlying Intelligent System Design strategy to
deliver software, hardware and IP that turn design concepts into
reality. Cadence customers are the world’s most innovative
companies, delivering extraordinary electronic products from chips
to boards to systems for the most dynamic market applications,
including consumer, hyperscale computing, 5G communications,
automotive, mobile, aerospace, industrial and healthcare. For seven
years in a row, Fortune magazine has named Cadence one of the 100
Best Companies to Work For. Learn more at cadence.com.
About PCI-SIG
PCI-SIG is the consortium that owns and manages PCI
specifications as open industry standards. The organization defines
industry standard I/O (input/output) specifications consistent with
the needs of its members. Currently, PCI-SIG is comprised of over
830 industry-leading member companies. To join PCI-SIG, and for a
list of the Board of Directors, visit www.pcisig.com.
© 2021 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, the Cadence logo and the other Cadence marks
found at www.cadence.com/go/trademarks are trademarks or registered
trademarks of Cadence Design Systems, Inc. PCI-SIG, PCI Express,
and PCIe are registered trademarks of PCI-SIG. All other trademarks
are the property of their respective owners.
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